In order to meet ever-increasing needs of the users for superior performance and low costs, there is a requirement for high integration density of semiconductor memory devices. In case of conventional two-dimensional semiconductor memory devices, their integration density is mainly determined by an area occupied by a unit memory cell. Therefore, the conventional two-dimensional semiconductor memory devices are greatly affected by fine-pattern forming technologies. However, because extremely high-priced apparatuses are needed to achieve fine patterns, the integration density of two-dimensional semiconductor memory devices is still limited while continuing to increase.
Various technologies for three-dimensionally forming memory cells have been suggested to overcome the foregoing limitation. According to the technologies, three-dimensionally arranged memory cells allow an area of a semiconductor substrate to be used effectively. For this reason, integration density of the three-dimensional memory device becomes higher than that of a two-dimensional semiconductor device.